Instruction pipelining is a commonly used technique in the design of computers and other digital electronic devices to increase instruction throughput. The fundamental idea is to split the processing of an instruction into a series of independent steps. A basic five-stage instruction pipeline contains the following stages: Instruction Fetch, Instruction Decode, Execute, Memory Access, and Write Back. Instruction pipelining allows the instructions to be issued at the processing rate of the slowest step, which may be faster than the time needed to perform all the steps at once.
A branch instruction causes a program to conditionally branch to another section of program code. It is not known whether the branch will be taken until the branch instruction has been executed, so the “next” instruction cannot enter the Fetch stage until after the branch instruction has passed the Execute stage. One way to handle branch instructions in the presence of instruction pipelining is branch prediction, i.e., predicting whether the branch will be taken and fetching the next instruction based on the prediction. However, if it turns out that the branch has been mispredicted, all the instructions in the pipeline following the branch instruction have to be flushed and the correct instruction has to be fetched (typically referred to as “mispredict penalty”).
Instruction predication enables an instruction to conditionally perform or do nothing. Thus, in the context of branch prediction, if a branch is mispredicted, the instructions in the pipeline after the branch can be “turned off” (e.g., treated like no-ops) instead of being flushed. Instruction predication is commonly accomplished by using predicate registers to store the value of the branch condition when the branch instruction passes the Execute stage. The predicate registers act like a third operand for an instruction. The instruction may be executed or ignored depending on the value in the predicate register. However, using predicate registers for instruction predication may require an additional predicate register field in the instruction format. Having an additional field in the instruction format may use valuable opcode and/or register address space in instruction words.